Mixed-signal circuits are sensitive to transistor mismatch. The well known Pelgrom model has demonstrated that the variation between two devices on the same die due to random mismatch is inversely proportional to the square root of the device area. Since transistor mismatch effects grow worse with shrinking transistor sizes, mismatch effects have become a dominant yield and performance limiting factor in high speed mixed-signal circuit designs. Such mismatch effects makes it increasingly difficult for analog and radio frequency (RF) circuits to benefit from the transistor scaling available at each new process technology node. While some approaches have been developed to counter mismatch effects, they all suffer from various limitations.
For example, adaptive body bias (ABB) techniques have been applied to digital circuit operation to provide post processing adjustment for die-to-die and within die variation. However, most of the development effort has been directed to the implementation and adjustment of one or more complex analog body bias generators to create precision analog voltages to perform the body bias adjustments needed. It is presumed that similar techniques could be applied to mixed-signal circuits at the expense of adding multiple area consuming analog body bias generators, which must be routed to each critical sub-circuit node body terminal.
Alternatively, for analog circuits, a technique has been proposed involving the physical implantation of multiple differential pairs connected in parallel and selecting the subset which achieves the desired level of matching. This approach has major limitations in excess silicon area and added gate capacitance.